Physically meaningful and easy-to-use analytical predictive stress models are developed for a through-silicon-via (TSV) design using theory-of-elasticity based approach. Two extreme cases of the TSV height-to-diameter ratios are considered: disc-like vias, with the aspect ratios below 0.25 (plane stress approximation can be employed in this case), and rod-like-vias, with aspect ratios, above 2.5 (plane strain approximation is applicable in this case). The objectives of the analysis are 1) to evaluate the effect of the size of the opening in the silicon (Si) material on the pressure at its boundary with the disc/rod, when the TSV structure is heated up, and the Si material is in tension because of the elevated circumferential stresses, and 2...
In this paper we report experimental results of through silicon vias (TSVs) at an early processing s...
This paper is concerned with the thermal mechanical stability of 3D TSV with initial thermal stress ...
Continual scaling of devices and on-chip wiring has brought significant challenges for materials and...
The reported failure of the Cu-filled via adjacent to the SiO2 liner of a TSV interconnect under the...
As multiple layers of planar device are stacked to alleviate signal delay problem and reduce chip ar...
In 3-D interconnect structures, process-induced thermal stresses around through silicon vias (TSVs) ...
In 3-D interconnect structures, process-induced thermal stresses around through silicon vias (TSVs) ...
Through-silicon via (TSV) is a critical element connecting stacked dies in three-dimensional (3D) in...
Through-silicon via (TSV) is a critical element connecting stacked dies in three-dimensional (3D) in...
Thermal conduction and mechanical stresses in through silicon via (TSV) structures in three dimensio...
Thermal conduction and mechanical stresses in through silicon via (TSV) structures in three dimensio...
In 3-D interconnect structures, process-induced thermal stresses around through-silicon-vias (TSVs) ...
Through-silicon via (TSV) is one of the emerging technology enablers for the 3D Interconnects. TSV c...
Through-silicon via (TSV) is one of the emerging technology enablers for the 3D Interconnects. TSV c...
One approach to 3D chip stacking and integration is to process filled Cu-vias into the Si and to att...
In this paper we report experimental results of through silicon vias (TSVs) at an early processing s...
This paper is concerned with the thermal mechanical stability of 3D TSV with initial thermal stress ...
Continual scaling of devices and on-chip wiring has brought significant challenges for materials and...
The reported failure of the Cu-filled via adjacent to the SiO2 liner of a TSV interconnect under the...
As multiple layers of planar device are stacked to alleviate signal delay problem and reduce chip ar...
In 3-D interconnect structures, process-induced thermal stresses around through silicon vias (TSVs) ...
In 3-D interconnect structures, process-induced thermal stresses around through silicon vias (TSVs) ...
Through-silicon via (TSV) is a critical element connecting stacked dies in three-dimensional (3D) in...
Through-silicon via (TSV) is a critical element connecting stacked dies in three-dimensional (3D) in...
Thermal conduction and mechanical stresses in through silicon via (TSV) structures in three dimensio...
Thermal conduction and mechanical stresses in through silicon via (TSV) structures in three dimensio...
In 3-D interconnect structures, process-induced thermal stresses around through-silicon-vias (TSVs) ...
Through-silicon via (TSV) is one of the emerging technology enablers for the 3D Interconnects. TSV c...
Through-silicon via (TSV) is one of the emerging technology enablers for the 3D Interconnects. TSV c...
One approach to 3D chip stacking and integration is to process filled Cu-vias into the Si and to att...
In this paper we report experimental results of through silicon vias (TSVs) at an early processing s...
This paper is concerned with the thermal mechanical stability of 3D TSV with initial thermal stress ...
Continual scaling of devices and on-chip wiring has brought significant challenges for materials and...