Exploratory Efforts to Manage Power-Aware Memories using Software Generated Hints

This report presents our exploratory efforts for managing main memory power-aware chips. Current state-of-the-art power-aware DRAM chips offer various power modes (active, standby, nap, and powerdown) in order to provide a potential to limit power consumption in the face of increasing demand for performance. Our goal in this study is to utilize and exploit these various power modes for the most effective main memory power management under software control in response to workloads becoming increasingly memory-intensive and data-centric