Design of a full 1Mb STT-MRAM based on advanced FDSOI technology

In one hand, the shrinking of CMOS technology nodes is dramatically increasing the leakage current in integrated circuits. In the other hand, modern portable devices first concern is power-efficiency to insure a better autonomy. Thus, new device technologies and computing strategies are required in integrated systems to save power without limiting processing performances. The use of Non-Volatile Memories (NVM) seems to be a choice of a great interest in complex computing systems. But, their integration within heterogeneous technologies remains a real challenge. Among emerging NV memories, Spin Transfer Torque Magnetic Random Access Memories (STT-MRAM) is considered as one of the most attractive candidates to overcome shortcomings of conventional memories. In this paper, we describe the design of a fully embedded STT-MRAM. We developed and validated a complete MRAM platform to simulate and evaluate a 1Mb STT-MRAM based on 28nm FDSOI technology. Furthermore, we exploited body back biasing techniques offered by the FDSOI technology to achieve 60% of decrease in term of leakage power and give the possibility to increase performance up to 2x