With the exponential improvement in integrated circuit technology comes the problem of how to design systems containing millions of devices. This thesis presents a new look at hierarchical design based on the Caltech structured design methodology. The hierarchy is separated into two parts: leaf cells, containing no instances of other cells, and composition cells, containing only instances of other cells. A leaf cell can be implemented in many different representations. A representation consists of a set of leaf cells and a composition rule that builds correct higher level cells. The separated hierarchy is suitable for mathematical analysis by the use of Curry's theory of combinators. In this form, a hierarchy is represented by a mathe...
This paper describes a uniform and new approach to a technology independent and hierarchical artwork...
This book examines seven key combinatorial engineering frameworks (composite schemes consisting of a...
We present a hierarchical methodology for ensuring functionally correct VLSI designs. This methodolo...
With the exponential improvement in integrated circuit technology comes the problem Of how to design...
A transistor level representation for VLSI circuits is presented. This representation is simple but ...
The nature of hierarchical design tools for VLSI implementation is explored in terms of the "Caltec...
technical reportThis dissertation presents a new design environment for VLSI circuits that is based ...
This paper describes the hierarchical design process for VLSI circuits and discusses the potential ...
This thesis describes a new approach to the problem of Geometrical Design Rule Checking (DRC). Previ...
Recent developments in the technology of fabricating large-scale integrated circuits have made it po...
The use of hierarchical abstractions allows processing at an abstract level so that the complexity o...
We define a notion of equivalence for designs containing black boxes. Using this notion, we describe...
International audienceThis paper deals with hierarchical design, component re-use and more generally...
This report describes the algorithm, implementation, and performance of a hierarchical circuit extr...
ABSTRACT: In computer-aided biological design, the trifecta of characterized part libraries, accurat...
This paper describes a uniform and new approach to a technology independent and hierarchical artwork...
This book examines seven key combinatorial engineering frameworks (composite schemes consisting of a...
We present a hierarchical methodology for ensuring functionally correct VLSI designs. This methodolo...
With the exponential improvement in integrated circuit technology comes the problem Of how to design...
A transistor level representation for VLSI circuits is presented. This representation is simple but ...
The nature of hierarchical design tools for VLSI implementation is explored in terms of the "Caltec...
technical reportThis dissertation presents a new design environment for VLSI circuits that is based ...
This paper describes the hierarchical design process for VLSI circuits and discusses the potential ...
This thesis describes a new approach to the problem of Geometrical Design Rule Checking (DRC). Previ...
Recent developments in the technology of fabricating large-scale integrated circuits have made it po...
The use of hierarchical abstractions allows processing at an abstract level so that the complexity o...
We define a notion of equivalence for designs containing black boxes. Using this notion, we describe...
International audienceThis paper deals with hierarchical design, component re-use and more generally...
This report describes the algorithm, implementation, and performance of a hierarchical circuit extr...
ABSTRACT: In computer-aided biological design, the trifecta of characterized part libraries, accurat...
This paper describes a uniform and new approach to a technology independent and hierarchical artwork...
This book examines seven key combinatorial engineering frameworks (composite schemes consisting of a...
We present a hierarchical methodology for ensuring functionally correct VLSI designs. This methodolo...