Comprehensive study on random access memory testing : from test pattern generation algorithm to MBIST implementation

Semiconductor memory is one the most important microelectronic components in digital system design. Embedded memories have used up more than 20 percent of the silicon fabricated area in most of the consumer products. This revolution is calling for ever-increasing trend to reduce Defect Per Million (DPM) levels of memories requires tests with high fault coverage and low cost. The conventional way to test a memory, researchers have to use C like programming to generate the test patterns, convert test pattern to tester vector in pre-silicon validation to generate the golden signature. The final step is to convert the pre-silicon test to tester language for silicon validation. This project introduces standalone MBIST hardware solution to generate RAM addresses, test patterns and test sequences according to C generated March test algorithm to reduce complicated steps along silicon validation. MBIST platform is able to test synchronized single port configurable Random Access Memory (RAM) up to eight data width and 64 address entries. This work has been implemented using Verilog Hardware Description Language (HDL) and verified using Mentor Graphic Modelsim tool. Simulation results have shown good agreement with the expected results