Hardware implementation of data acquisition for the construction of histogram in real time

The goal of this thesis is to design architecture for real-time histogram building application on Xilinx Virtex 5 FPGA and to implement it. Thesis presents the problem we are solving and its solution. The emphasis is on architecture design and problem analisys of the implementation process. Histogram building in real time is a problem of processing large amount of data, which is acquired in real time. For practical use of this data we need to implement an application for that purpose. There are many possible architectural solutions for that problem and we will concentrate on one of them. In the process of implementation in VHDL programming language we will solve the problem of signal time domain crossing and the problems of using either »white box« or »black box« subsystems. We will conclude the thesis with a presentation and an analisys of the results. We will plot the recieved data as histograms and on that basis we will conclude that we have successfully completed our project. We will also establish that background noise is a source of problems in electronic circuits, especially due to high resolution of the histogram