Modelling and simulation of hot-carriers degradation of high voltage floating lateral NDMOS transistors

This paper presents the Hot Carrier Endurance of a High Voltage (100V) self aligned Floating lateral nDMOS transistor. Based on experimental results, a Safe Operating Area is determined according to maximum 10% shift of electrical parameters within 25 years. Process/Device simulation has been done in order to understand the degradation phenomena based on bulk current. Two points of high Impact Ionization rates have been found : one close to the channel junction but in depth, and the second one in the drift region. This later explains the Hot Carrier Degradation of the Ron parameter observed experimentally