Row-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion paradigm between cell-level and block-level granularity, in which each layout row defines the unit of gating, and different rows can be clustered and share the same sleep transistor. Previous works, however, assume the availability of a single virtual ground voltage, thus making the decision of whether to gate or not a given cluster a binary choice: a cluster is either gated or not. In this work, we consider a limited set of virtual ground voltages, which allows us to assign to a cluster the virtual ground voltage that offers the best leakage-performance tradeoff for that cluster. We propose two algorithms for solving two power-gating variants: on...
Leakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and ind...
[[abstract]]One of the effective techniques to reduce leakage power is power gating. Previously, a D...
This paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. Our ...
Row-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion parad...
In this paper we focus on leakage reduction through automatic insertion of sleep transistors using a...
Leakage power has become a serious concern in nanometer CMOS technologies, and power-gating has show...
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage...
The use of sleep transistors as power-gating elements to cut-off sub-threshold leakage stand-by curr...
[[abstract]]System-on-a-chip with multiple power domains reduces leakage power consumption by power ...
[[abstract]]Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Tr...
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce ...
[[abstract]]Power gating is an efficient technique for reducing leakage power in electronic devices ...
A very popular approach for leakage power reduction is today represented by the adoption of emerging...
FPGAs are being increasingly used in a wide variety of ap-plications. While power optimization has b...
Power-gating is one of the most promising and widely adopted solutions for controlling sub-threshold...
Leakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and ind...
[[abstract]]One of the effective techniques to reduce leakage power is power gating. Previously, a D...
This paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. Our ...
Row-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion parad...
In this paper we focus on leakage reduction through automatic insertion of sleep transistors using a...
Leakage power has become a serious concern in nanometer CMOS technologies, and power-gating has show...
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage...
The use of sleep transistors as power-gating elements to cut-off sub-threshold leakage stand-by curr...
[[abstract]]System-on-a-chip with multiple power domains reduces leakage power consumption by power ...
[[abstract]]Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Tr...
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce ...
[[abstract]]Power gating is an efficient technique for reducing leakage power in electronic devices ...
A very popular approach for leakage power reduction is today represented by the adoption of emerging...
FPGAs are being increasingly used in a wide variety of ap-plications. While power optimization has b...
Power-gating is one of the most promising and widely adopted solutions for controlling sub-threshold...
Leakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and ind...
[[abstract]]One of the effective techniques to reduce leakage power is power gating. Previously, a D...
This paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. Our ...