Reconfigurable coprocessor based JPEG 2000 implementation

This paper proposes a reconfigurable coprocessor based implementation for the forthcoming standard JPEG 2000 for still images. First a preliminary overview of the standard, mainly focusing on the major characteristics of the different functional units, is presented. Then results obtained by a profile analysis are shown and a partition between DSP and FPGA is proposed for the implementation of a codec architecture. Finally the most critical units in terms of required computation effort, have been mapped on FPGA devices in order to preserve an high degree of reconfigurability. It is worth noticing that to the best of our knowledge only software implementations of JPEG 2000 has been produced yet