Design and implementation of low-power CMOS analogue convolutional decoders using the modified feedback decoding algorithm

Convolutional decoders are very important in digital communication systems, especially in applications where very high noise levels are introduced on the information signal by wireless transmission. Examples of such systems are satellite communications, cellular telephony and digital audio broadcasting (DAB). The most commonly employed decoding method so far in convolutional codes has been the Viterbi algorithm (VA), mainly implemented in digital hardware to accommodate large memory requirements. In this thesis an introduction to convolutional codes and basic digital communication systems is given, followed by an in depth study of the VA and possible Viterbi decoder (VD) implementations. Advantages and limitations are identified in existing analogue VD designs. A recently proposed algorithm, known as the modified feedback decoding algorithm (MFDA), is then presented and clarified. The MFDA incorporates certain key features of the VA while it requires no digital memory and therefore lends itself to an entirely analogue implementation. This in turn improves performance characteristics, effectively trading complexity and power dissipation against operating speed. The first ever realisation of the novel MFDA is also presented here. Firstly, extensive system-level simulations model errors arising from the use of analogue circuits in practical convolutional decoders. Consequently, and based on these results, a mixed-signal hard-decision modified feedback decoder (MFD) is designed as a proof of principle, using the Austriamicrosystems (AMS) CMOS 0.6pm technology. The fabricated chips have 100% yield and measured results indicate that there is a negligible loss in coding performance compared with a VD. This work can potentially launch the advent of future miniaturised ultra low power analogue convolutional decoders