An efficient cut enumeration for depth-optimum technology mapping for lut-based fpgas

Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size con-sumes run-time very much. The number of cuts exponen-tially increases with the size of cuts, which causes long run-time. Furthermore, an ineciency of bottom-up merging in existing algorithms makes the run-time much longer. This paper presents a novel cut enumeration. The proposed algo-rithm is ecient because it enumerates cuts without bottom-up merging. Our algorithm has two modes; exhaustive enu-meration and partial enumeration. Exhaustive enumeration enumerates all cuts. Partial enumeration enumerates partial cuts with a guarantee that a depth-minimum network can be constructed. The experimental results show that exhaus-tive enumeration runs about 3 times and 8 times faster than existing bottom-up algorithm [1] [2] for K = 8, 9, respec-tively. The quality of network are the same. Furthermore, partial enumeration runs about 6 times and 18 times faster than bottom-up algorithm for K = 8, 9, respectively. Area of network derived by the set of cuts enumerated by partial enumeration is only 4 % larger than that derived by exhaus-tive enumeration on average, and the depth is the same