ISSCC95 1 SESSION ATA CONVERTERS 1 PAPER FA 16.3 I

In bipolar technology the folding and interpolation technique has proven to be successful for high sample rates [l,2l. This paper investigates the possibilities of this technique in CMOS. The major advantage of folding and interpolation in CMOS lies in the field of high sample rate in combination with low power consump-tion and small chip area. The folding converter requires little power to drive the input compared to other convertem since the input behaves like a linear and constant capacitor [6]. For similar reasons the power consumption of the reference ladder of the folding converter can be kept low. 8b CMOS designs reported in References 3 and 4 achieve 85MSamplds and 100MSamplds respectively. Both designs however have a power dissipation of more than lW, too much for embedded applications. The circuit reported here runs at 7OMSamplds and dissipates only 1lOmW. Figure 1 shows the architecture of the ADC. The converter can b