Performance Evaluation of Multi-Core Architectures in Training and Simulation: A Case Study with AMD and Intel Dual-Core Systems

The defence tra ining and simulation industry is increasingly us ing server CPUs for processing data. Distributed simulation data creates a large number of small packets t hat m ust be proc essed at t he n etwork level be fore t he hig her l evel simulation p rocessing is pe rformed. A s ne twork traffic in creases i t becomes a burden on the server CPUs, which need to process more packets and still have room f or application s oftware. M ulti-core proc essor sys tems are be ing introduced as a solution to the increase in processor utilization. In this work, we evaluate the pe rformance of ser vers ba sed on the dua l-core A MD O pteron a nd the d ual-core I ntel X eon processors while e xecuting in a typi cal di stributed simulation environment. First, we illustrate the high processing power needed to process a n etwork stream with small pa cket si zes. S econd, we spe cify the differences between two major competitors in the server chip market, Intel's dual-core Xeon processor and AMD's dual-core Opteron processor. We then test the maximum throughput of servers out fitted with the chips against a ba seline dual single-core proc essor I ntel se rver. T he tests us e t hree s eparate l og f iles t o characterize the effect that packet size has on the network throughput. Log files are us ed to make t he t est reproducible and ar e ge nerated from t he a ctual simulation along with the network simulation