Chapter # ON-CHIP STOCHASTIC COMMUNICATION

Abstract: As CMOS technology scales down into the deep-submicron (DSM) domain, the Systems-On-Chip (SoCs) are getting more and more complex and the costs of design and verification are rapidly increasing due to the inefficiency of traditional CAD tools. Relaxing the requirement of 100 % correctness for devices and interconnects drastically reduces the costs of design but, at the same time, requires that SoCs be designed with some degree of system-level fault-tolerance. In this chapter, we introduce a new communication paradigm for SoCs, namely stochastic communication. The newly proposed scheme not only separates communication from computation, but also provides the required built-in fault-tolerance to DSM failures, is scalable and cheap to implement. For a generic tile-based architecture, we show how a ubiquitous multimedia application (an MP3 encoder) can be implemented using stochastic communication in an efficient and robust manner. More precisely, up to 70% data upsets, 80 % packet drops because of buffer overflow, and severe levels of synchronization failures can be tolerated while maintaining a much lower latency than a traditional bus-based implementation of the same application. We believe that our results open up a whole new area of research with deep implications for on-chip network design of future generations of SoCs