High-Speed and Low-Power Architectures for Forward and Inverse Discrete Wavelet Transform Using 4-Tap Daubechies Filters

This paper presents two architectures for 2-D discrete wavelet transform (DWT) and inverse DWT (IDWT). The first consists of transform module, RAM module and address sequencer. The transform module, which takes uniform and regular structure with local communication, offers many advantages, e.g. simple control flow, full hardware-utilization and low-power. The second architecture features parallel and pipelined computation for high throughput. Both architectures are suitable for VLSI implementations of the wavelet based image coders, e.g. JPEG-2000. The FPGA realization and VLSI implementation of the proposed 2-D DWT/IDWT architectures with 4-tap Daubechies filters shows significant improvements in terms of power saving and chip area