류지구1,+·김남호2·정수태1 Magnetic Sensitivity Improvement of Silicon Vertical Hall Device

The silicon vertical hall devices are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-SiO2 ¸ interface and n-epi layer without n+ buried layer to improve the sensitivity and influence of interface effects. Experimental samples are a sensor type I with and type H without p+isolation dam adjacent to the center current electrode. The experimental results for both type show a more high current-related sensitivity than the former's vertical hall devices. The sensitivity of type H and type I are about 150 V/AT and 340 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model