Energy-efficient and metastability-immune timing-error detection and instruction-replay-based recovery circuits for dynamic-variation tolerance

Abstract—A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection se-quential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. One EDS circuit is a dynamic transition detector with a time-borrowing datapath latch (TDTB). The other EDS circuit is a double-sampling static design with a time-borrowing datapath latch (DSTB). In comparison to previous EDS designs, TDTB and DSTB redirect the highly com-plex metastability problem from both the datapath and error path to only the error path, enabling a drastic simplification in man-aging metastability. From a survey of various EDS circuit options, TDTB represents the lowest clock energy EDS circuit known; DSTB represents the lowest clock energy static-EDS circuit with SER protection known. Error-recovery circuits are introduced to replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, test-chip measurements demonstrate that resilient circuits enable either 25%–32 % throughput gain at equal or at least 17 % reduction at equal throughput, corresponding to 31%–37 % total power reduction. Index Terms—Dynamic variations, error correction, error detection, error-detection sequential, error recovery, instruction replay, parameter variations, resilient circuits, resilient design, supply voltage droop, temperature variation, timing errors, varia-tion tolerance. I