Simulation of Gate Coupling Effect on Three- Dimensionally Stacked Devices

In two-dimensional integrated circuits (2-D IC), new technologies have decreased the device feature size and improved the circuit performance. However, due to not only the scaling limit but also the increase of resistive capacitive delay of very large scale integration (VLSI) technology, a further increase of device density will depend on the theree-dimensional intergration technology[1]. The three-dimensional integrated circuit (3-D IC) for advanced CMOS application has a significant potential and several advantages, such as reduction of delay, power consumption, and increase of packing density by reducing the parasitic resistance and interconnection length, minimization of chip area due to the multi-layer integration on a single chip, and so on[2],[3]