Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power gating technique

One of the benefits of coarse grained dynamically re-configurable processor array(DRPA) is its low dynamic power consumption by operating a number of processing elements(PE) in parallel with low clock frequency. How-ever, in the future advanced processes, leakage power will occupy a considerable part of the total power consumption, and it may degrade the advantage of DRPAs. In order to re-duce the leakage power, a fine grained Power Gating(PG) is applied to a DRPA, MuCCRA-2.32b, and leakage power and area overhead are measured. We evaluated the effect of two control modes; Pair and Unit Individual based on layout design and real applications. It appears that by ap-plying PG for ALUs and SMUs in PEs individually, 48 % of leakage power can be reduced with 9.0 % of area overhead. 1