Advisor

In today’s world of advanced technology, numerous applications are computational intensive. This led to the development of new System-on-Chip (SoC) design techniques to allow for integration and reuse of Intellectual Property, IP Cores, under time-to-market pressure. A wide range of these newly emerging design platforms is now drifting towards highly integrated SoC designs with many on-chip processing resources like processors, DSPs, and memory. Using this technique, designers can build SoC by integrating dozens of IP cores. As the number of IP cores increases, the on-chip communication and physical interconnections become a bottleneck. Originally, SoC was built based on a Bus-Centered approach. The Bus-Centered approach is a shared-medium architecture in which all IP cores share the same transmission medium. The Bus architecture is widely used in current SoC implementation and will continue to be the right design platform for small designs that integrate a few IP cores. However, for designs targeting FPGA with a large number of IP cores, we will propose a Micronetwork based System-on-FPGA (SoFPGA