ABSTRACT Title of dissertation: Optimization Schemes for Variability-Driven VLSI Design Automation

Today’s IC design is facing several challenges due to increasing circuit complex-ity and decreasing feature size, as it pushes to extend Moore’s law into nano-scale dimensions. Apart from the challenges that arise directly as a result of feature scaling (e.g., increasing leakage power, reliability issues), imperfections in the man-ufacturing process have recently turned into a major design hurdle, due to the varia-tions they cause in the device and interconnect parameters from their target values. From an IC design automation perspective, a shift in paradigm, from deterministic to probabilistic, is needed to handle the unpredictable nature of these fabrication variations. In such a probabilistic paradigm, the varying circuit parameters such as leakage power or delay should be accurately modeled, and their correlations due to com-mon sources of variations or physical location on the chip should be well captured. Moreover, variability-driven (probabilistic) design automation needs to efficiently generate a high quality solution. A particular challenge in variability-driven design automation is to define op