Abstract—In this paper, we present a novel cache scheme which efficiently reduces the minimum operating voltage (Vmin) despite manufacturing-induced defective SRAM cells. The proposed low-voltage scheme exploits the fact that locations of defective SRAM cells are usually non-uniformly scattered. It also leverages the reliable characteristics of 7T/14T SRAM and allows associativites in each index to be different. Our evaluation results show that the proposed cache can reduce Vmin of 64 KB 8-way set-associative cache by 80 mV within 7.81 % capacity and 5.22 % area overhead. I
Transistors per area unit double in every new technology node. However, the electric field density a...
Abstract—Power density has become the limiting factor in technology scaling as power budget limits t...
SRAM based cache becomes a more critical source of power dissipation, particularly for large last le...
This paper presents a novel cache architecture using 7T/14T hybrid SRAM, which can dynamically impro...
Abstract-this paper proposes a novel Process Variation Aware SRAM architecture designed to inherentl...
Abstract. Power consumption is becoming one of the most important con-straints for microprocessor de...
To continue reducing voltage in scaled technologies, both circuit and architecture-level resiliency ...
This thesis presents a novel six-transistor SRAM intended for advanced microprocessor cache applicat...
textOne of the major limiters to computer systems and systems on chip (SOC) designs is accessing the...
One of the most effective techniques to reduce a processor\u27s power consumption is to reduce suppl...
Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scali...
Abstract—In this paper we present the “Variation Trained Drowsy Cache ” (VTD-Cache) architecture. VT...
Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scali...
Aggressive scaling of transistor dimensions with each technology generation has resulted in increase...
4th International Workshop on Dependable Embedded Systems : October 9, 2007 : Beijing, ChinaLeakage ...
Transistors per area unit double in every new technology node. However, the electric field density a...
Abstract—Power density has become the limiting factor in technology scaling as power budget limits t...
SRAM based cache becomes a more critical source of power dissipation, particularly for large last le...
This paper presents a novel cache architecture using 7T/14T hybrid SRAM, which can dynamically impro...
Abstract-this paper proposes a novel Process Variation Aware SRAM architecture designed to inherentl...
Abstract. Power consumption is becoming one of the most important con-straints for microprocessor de...
To continue reducing voltage in scaled technologies, both circuit and architecture-level resiliency ...
This thesis presents a novel six-transistor SRAM intended for advanced microprocessor cache applicat...
textOne of the major limiters to computer systems and systems on chip (SOC) designs is accessing the...
One of the most effective techniques to reduce a processor\u27s power consumption is to reduce suppl...
Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scali...
Abstract—In this paper we present the “Variation Trained Drowsy Cache ” (VTD-Cache) architecture. VT...
Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scali...
Aggressive scaling of transistor dimensions with each technology generation has resulted in increase...
4th International Workshop on Dependable Embedded Systems : October 9, 2007 : Beijing, ChinaLeakage ...
Transistors per area unit double in every new technology node. However, the electric field density a...
Abstract—Power density has become the limiting factor in technology scaling as power budget limits t...
SRAM based cache becomes a more critical source of power dissipation, particularly for large last le...
Add to ORKG