A method is introduced for Cu bottom-up filling at trenches with dimensions similar to those of through silicon via in the presence of three organic additives. The electrodeposition is galvanostatically conducted, and the potential-time curves during the gap-filling and the evolution of deposition profiles according to the deposition time are investigated to clarify the mechanism of the Cu bottom-up filling. The role of each organic additive is examined by electrochemical analyses and the gap-filling profiles with various combinations of organic additives. Based on the results, the gap-filling mechanism regarding the surface coverages of organic additives is suggested. The bottom-up filling of Cu is achieved with the establishment of growin...
Copper electro-chemical deposition (ECD) of through silicon via (TSV) is a key challenge of 3D integ...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
We present two approaches to reduce the process time needed for filling vias of 5 µm diameter and 25...
In this work, the Cu electrodeposition was carried out for the filling of through silicon via (TSV) ...
A model for copper electroplating of through-silicon vias (TSV) is proposed based on the suppressor ...
Cu electroplating has been researched to form the interconnect in integrated circuits. A suppressor ...
3D integration with TSVs (Through Silicon Via) is emerging as a promising technology for the next ge...
The filling of microvias with a diameter of 5 µm and a depth of 25 µm (aspect ratio of 5) by copper ...
In the recent years, there has been a growing interest in micro- and nano-structured composite syste...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
Nowadays, high performance of integrated circuits is owing its interconnections and packaging techno...
There is an increasing demand for electronic devices with smaller sizes, higher performance and incr...
To enable low power consumption and the access speed increase, three dimensional packaging of semico...
The background of this paper is the fabrication of Through Silicon Vias (TSV) for three-dimensional ...
This work explores the mechanism of microvia filling by copper electroplating using a printed circui...
Copper electro-chemical deposition (ECD) of through silicon via (TSV) is a key challenge of 3D integ...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
We present two approaches to reduce the process time needed for filling vias of 5 µm diameter and 25...
In this work, the Cu electrodeposition was carried out for the filling of through silicon via (TSV) ...
A model for copper electroplating of through-silicon vias (TSV) is proposed based on the suppressor ...
Cu electroplating has been researched to form the interconnect in integrated circuits. A suppressor ...
3D integration with TSVs (Through Silicon Via) is emerging as a promising technology for the next ge...
The filling of microvias with a diameter of 5 µm and a depth of 25 µm (aspect ratio of 5) by copper ...
In the recent years, there has been a growing interest in micro- and nano-structured composite syste...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
Nowadays, high performance of integrated circuits is owing its interconnections and packaging techno...
There is an increasing demand for electronic devices with smaller sizes, higher performance and incr...
To enable low power consumption and the access speed increase, three dimensional packaging of semico...
The background of this paper is the fabrication of Through Silicon Vias (TSV) for three-dimensional ...
This work explores the mechanism of microvia filling by copper electroplating using a printed circui...
Copper electro-chemical deposition (ECD) of through silicon via (TSV) is a key challenge of 3D integ...
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced ...
We present two approaches to reduce the process time needed for filling vias of 5 µm diameter and 25...