APB Sub-sytem 3-D Stacked Memory System Architecture Exploration by ESL Virtual Platform and Reconfigurable Stacking Memory Architecture in 3D-DSP SoC System

Three-dimensional (3-D) integration promises continuous system-level functional scaling beyond the traditional 2-D device-level geometric scaling. It allows stacking memory dies on top of a logic die using through-silicon vias (TSVs) to realize high bandwidth by deploying the vertical connections between functional blocks. In this paper, we present a design strategy using ESL virtual platform to explore 3-D memory architecture for a heterogeneous multi-core system and base on exploration results, we propose the reconfigurable stacking memory architecture for three-dimension IC. Based on the virtual platform, designers can rapidly obtain the 3-D stacking interface for better system performance and TSV utilization. A feasible stacking architecture and memory interface which meets the design constraints and performance requirements has been evaluated for the target system. To demonstrate our 3-D IC design techniques, the stacking memory approach is employed in our “3D-DSP ” design. In 3D-DSP, we stack 512KB SRAM directly on top of the logic die which is heterogeneous multi-core computing platform for multimedia application purpose. The logic and memory dies are fabricated in the TSMC 90nmG 1P9M CMOS process. Finally, we use 3D-DSP EVB to demonstrate the performance improvement. Real multimedia H.264 decoding experiment shows that the stacking system can achieve about 66.4 % performance improvement compared to the original 2-D system. I