Digital Substrate Noise Reduction by Low-Power Circuit Operation and SOI Technology

Progress of integrated circuit technology allows integra-tion of analog and digital circuits on the same chip. This co-integration yields higher performances and reliability, while reducing power consumption, but also raises new challenges for circuit designers. The substrate noise gener-ated by the switching digital part has detrimental effects on the analog part. In this contribution, a wide-band charac-terization of the so-called “digital substrate noise ” is real-ized, in bulk and in SOI technology. The impact of low-power circuit operation mode on the digital substrate noise is investigated. A comparison of bulk and SOI technology with regard to the digital substrate noise level is also real-ized. 1