Through-Silicon Via Fill for 3D Interconnect Applications

etching silicon substrates to provide electrical connection for multi-chip interconnection and packaging for 3D systems. TSVs can provide shortest-length and highest-density connections with reduced signal delay and power consumption1,2. There are several steps preceding3 TSV fill in a 3D chip stacking integration scheme such as (a) dielectric insulation to isolate silicon from metal (b) deposition of copper diffusion barrier and copper seed. Post TSV filling steps include (c) excess metal removal by CMP and (d) wafer thinning. Achieving void free TSV filling is a critical and relatively difficult process. A robust TSV filling requires continuous seed coverage and appropriate plating conditions which include optimized plating bath and current wave forms. Utilization of a hard mask for etching vias i