Add to ORKGAbsrracr-A CMOS analog continuous-time delay line has been devel-oped composed of cascaded first-order current-domain all-pass sections. Each all-pass section consists of CMOS transistors and a single capacitor. The operation is based on the square-law characteristic of an MOS transistor in saturation. The delay time per section can either be controlled by an external voltage or locked to an external reference frequency by means of a control system which features a large capture range. Experi-mental verification has been performed on two setups: an integrated cascade of 26 identical all-pass sections and a frequency locking system breadboard built around two identical on-chip all-pass sections. I
A high efficient analog charge delay line (ACDL) is proposed in this paper. We can use these analog ...
A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution...
An asynchronous delay line for PAM signal having controlled delay capability is proposed. The delay ...
A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass se...
A current-domain first-order all-pass filter-section has been developed, composed of a single capaci...
Wireline signal processing circuits such as transversal equalizers rely on true time delay. An activ...
We have developed an adaptive delay system that adjusts the delay of a delay element so that it matc...
A programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is pro...
Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the d...
Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the d...
This paper describes the implementation of delay element using C4 band-pass filter for subband analo...
Design choices in CMOS analog signal processing circuits are presented. Special attention is focusse...
i l 'k-3 We have implemented a four-tap adaptive filter in a continuous-time analog VLSI circui...
A high efficient analog charge delay line (ACDL) is proposed. These analog delay lines can be used t...
The latest circuit provides a flexible architecture for analogue delay lines (ADL), which is useful ...
A high efficient analog charge delay line (ACDL) is proposed in this paper. We can use these analog ...
A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution...
An asynchronous delay line for PAM signal having controlled delay capability is proposed. The delay ...
A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass se...
A current-domain first-order all-pass filter-section has been developed, composed of a single capaci...
Wireline signal processing circuits such as transversal equalizers rely on true time delay. An activ...
We have developed an adaptive delay system that adjusts the delay of a delay element so that it matc...
A programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is pro...
Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the d...
Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the d...
This paper describes the implementation of delay element using C4 band-pass filter for subband analo...
Design choices in CMOS analog signal processing circuits are presented. Special attention is focusse...
i l 'k-3 We have implemented a four-tap adaptive filter in a continuous-time analog VLSI circui...
A high efficient analog charge delay line (ACDL) is proposed. These analog delay lines can be used t...
The latest circuit provides a flexible architecture for analogue delay lines (ADL), which is useful ...
A high efficient analog charge delay line (ACDL) is proposed in this paper. We can use these analog ...
A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution...
An asynchronous delay line for PAM signal having controlled delay capability is proposed. The delay ...