Add to ORKGWhile estimating glitches or spurious transitions is challenge due to signal correlations, the random behavior of logic gate delays makes the estimation problem even more clifficult. In this paper, we present statistical estimation of signal activity at the internal and output nodes of combini3tional and sequential CMOS logic circuits considering uncertainty of gate delay models. The methodology is based on the stochastic models of logic signals and the probabilistic behavior of gate delays due to process variations, interconnect parmitics, etc. We propose a statistical technique of estimating average-case activity, which is flexible in adopting different delay models and variations and can be integrated with worst-case analysis into statis...
The effect of interconnect coupling capacitance on neighboring CMOS logic gates driving coupled inte...
In the manufacturing of VLSI circuits, engineering designs should take into consideration random var...
A simple metric is presented for the accurate prediction of path delay variability within digital ci...
While estimating glitches or spurious transitions is challenge due to signal correlations, the rando...
Our aim is the development of a novel probabilistic method to estimate the power consumption of a co...
As mobile and portable information systems are becoming more popular, there is a need for the develo...
In this paper, we present accurate estimation of signal activity at the internal nodes of sequential...
Abstract—In nanoscale CMOS circuits the random dopant fluc-tuations (RDF) cause significant threshol...
Dynamic power dissipation of a CMOS VLSI circuit depends on the signal activity at gate outputs. The...
Reliability assessment is an important part of the design process of digital integrated circuits. We...
This paper presents accurate estimation of signal activity at the internal nodes of combinational lo...
Abstract—This paper presents novel techniques for timing yield optimization and for yield estimation...
This thesis focuses on random local delay variability measurement and its modeling. It explains a ci...
The effect of interconnect coupling capacitance on neighboring CMOS logic gates driving coupled inte...
The effect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gat...
The effect of interconnect coupling capacitance on neighboring CMOS logic gates driving coupled inte...
In the manufacturing of VLSI circuits, engineering designs should take into consideration random var...
A simple metric is presented for the accurate prediction of path delay variability within digital ci...
While estimating glitches or spurious transitions is challenge due to signal correlations, the rando...
Our aim is the development of a novel probabilistic method to estimate the power consumption of a co...
As mobile and portable information systems are becoming more popular, there is a need for the develo...
In this paper, we present accurate estimation of signal activity at the internal nodes of sequential...
Abstract—In nanoscale CMOS circuits the random dopant fluc-tuations (RDF) cause significant threshol...
Dynamic power dissipation of a CMOS VLSI circuit depends on the signal activity at gate outputs. The...
Reliability assessment is an important part of the design process of digital integrated circuits. We...
This paper presents accurate estimation of signal activity at the internal nodes of combinational lo...
Abstract—This paper presents novel techniques for timing yield optimization and for yield estimation...
This thesis focuses on random local delay variability measurement and its modeling. It explains a ci...
The effect of interconnect coupling capacitance on neighboring CMOS logic gates driving coupled inte...
The effect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gat...
The effect of interconnect coupling capacitance on neighboring CMOS logic gates driving coupled inte...
In the manufacturing of VLSI circuits, engineering designs should take into consideration random var...
A simple metric is presented for the accurate prediction of path delay variability within digital ci...