III-V-On-Insulator MOSFETs on Si Substrates fabricated by direct bonding technique

New device engineering is indispensable in overcoming difficulties of advanced CMOS under 10 nm regime. Particularly, MOSFETs using the carrier-transport-enhanced channels featuring low effective mass have been regarded as necessary for obtaining high current drive and low supply voltage [1]. From this viewpoint, strong attentions have recently been paid to III-V and Ge channels. Here, MOSFETs using these materials must be fabricated on Si substrates in order to fully utilize Si CMOS platform, meaning the necessity of the co-integration of III-V/Ge on Si. This heterogeneous integration is expected to realize novel LSIs utilizing a variety of device families along More-Moore, More-than-Moore and Beyond-CMOS approaches (Fig. 1). It should be noted here that, for logic CMOS applications unde