Add to ORKGAbstract — In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides a theoretical background to efficiently construct a buffered 3D clock tree that minimizes and balances the skew values under two distinct non-uniform thermal profiles. Our clock tree synthesis algorithm named BURITO (Buffered Clock Tree With Thermal Optimization) first constructs a 3D abstract tree tree is then embedded, buffered, and refined under the given non-uniform thermal profiles so that the temperature-dependent skews are minimized and balanced. Experimental results show that our algorithms significantly reduce and perfectly balance clock skew ...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
The thermal gradients existing in high-performance circuits may significantly affect their timing b...
jltsaiocae. wisc. edu Abstract- Zero-skew clock-tree.with minimum clock-delay is preferable due to i...
Thermal issues are a primary concern in the three-dimensional integrated circuit (3D IC) design. Thi...
Temperature variation in microprocessors is a workload dependent problem. In such a design, the cloc...
The existence of non-uniform thermal gradients on the substrate in high performance IC's can signifi...
In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total...
The trend of growing density on chips has increases not only the temperature in chips but also the g...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
3D physical design needs accurate device model of through-silicon vias (TSVs). In this paper, physic...
Clock tree synthesis plays an important role on the total performance of chip. Gated clock tree is a...
In this thesis, an optimization framework is proposed to synthesize clock trees with useful skews. T...
Abstract—Clock tree synthesis plays an important role on the total performance of chip. Gated clock ...
This work tackles a problem of clock power minimization within a skew constraint under supply voltag...
Chip heating and nonuniform distribution of hot and cool zones on the die negatively affect reliabil...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
The thermal gradients existing in high-performance circuits may significantly affect their timing b...
jltsaiocae. wisc. edu Abstract- Zero-skew clock-tree.with minimum clock-delay is preferable due to i...
Thermal issues are a primary concern in the three-dimensional integrated circuit (3D IC) design. Thi...
Temperature variation in microprocessors is a workload dependent problem. In such a design, the cloc...
The existence of non-uniform thermal gradients on the substrate in high performance IC's can signifi...
In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total...
The trend of growing density on chips has increases not only the temperature in chips but also the g...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
3D physical design needs accurate device model of through-silicon vias (TSVs). In this paper, physic...
Clock tree synthesis plays an important role on the total performance of chip. Gated clock tree is a...
In this thesis, an optimization framework is proposed to synthesize clock trees with useful skews. T...
Abstract—Clock tree synthesis plays an important role on the total performance of chip. Gated clock ...
This work tackles a problem of clock power minimization within a skew constraint under supply voltag...
Chip heating and nonuniform distribution of hot and cool zones on the die negatively affect reliabil...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
The thermal gradients existing in high-performance circuits may significantly affect their timing b...
jltsaiocae. wisc. edu Abstract- Zero-skew clock-tree.with minimum clock-delay is preferable due to i...