Design-time and Run-time Reconfigurable Clustered ρ-VEX VLIW Softcore Processor

Faculty of Electrical Engineering, Mathematics and Computer Science The ρ-VEX processor is a parameterized reconfigurable Very Large Instruction Word (VLIW) softcore processor. It can be reconfigured in the issue-width, number and type of functional units (FUs), width of memory buses and number of registers in the multi-ported register file. The current design of the ρ-VEX processor supports single cluster processor organization. The design also provides run-time dynamic reconfigurability between different processor architectures. As the issue-width of the processor increases, the number of read and write ports from the FUs to the register file increases which enlarges its area utilization. This increase in the number of read and write ports is not scalable with the interconnect wires available in the current IC technology. From literature, we know that clustering the FUs of the processor and splitting up the register file into a smaller subsets significantly reduces the area overhead and power consumption. In this thesis, we have developed all the necessary hardware and software components to enable the design-time and run-time reconfigurable ρ-VEX processors to suppor