FPGA 설계 FPGA based Implementation of FAST and BRIEF algorithm for Object Recognition 허 훈, 이 광 엽

This paper implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57 % of internal memory usage and 70 % of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per Clock