Abstract: Nowadays, three-dimensional network-on-chip (3D NoC) with its shorter global interconnects, higher perform-ance, lower loss of interconnection, higher packing density, smaller volume, and many other advantages, has drawn more and more attention in both industrial and academic circle. In this paper, an improved algorithm, named the algorithm based on particle swarm optimization algorithm to optimize the floorplans (PSO-NoC), has been proposed with simula-tions conducted to rectify this algorithm. The simulation results are compared with the original Simulated Annealing-NoC. The experimental results show that the PSO-NoC algorithm reduces the latency and improves the throughput com-pared with the original one. Particularly, the CPU’...
We propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh networ...
Floorplanning is an important physical design step for hierarchical, building-block design methodolo...
(3D-MPSoC) adoption. It is characterized by the integration of a large amount of hardware components...
Abstract: In this paper, an improved floorplanning algorithm, named the floorplanning algorithm base...
none5Three dimensional integration is a promising approach for reducing the form factor of chips. Sc...
Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-...
In the paper we describe P-medians searching algorithm for Three-dimensional (3D) Network-on-Chip (N...
Power optimization is an important part of network-on-chip(NoC) design. This paper proposes an impro...
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the ...
Quality of task scheduling is critical to define the network communication efficiency and the perfor...
Multi-core System-on-Chips (SoCs) are a promising research area due to their improved speed (due to ...
Constant necessity of improving performance has brought the invention of 3D chips. The improvement i...
Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip comm...
Three-dimensional integrated circuits are a promising approach to address the integration challenges...
Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration c...
We propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh networ...
Floorplanning is an important physical design step for hierarchical, building-block design methodolo...
(3D-MPSoC) adoption. It is characterized by the integration of a large amount of hardware components...
Abstract: In this paper, an improved floorplanning algorithm, named the floorplanning algorithm base...
none5Three dimensional integration is a promising approach for reducing the form factor of chips. Sc...
Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-...
In the paper we describe P-medians searching algorithm for Three-dimensional (3D) Network-on-Chip (N...
Power optimization is an important part of network-on-chip(NoC) design. This paper proposes an impro...
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the ...
Quality of task scheduling is critical to define the network communication efficiency and the perfor...
Multi-core System-on-Chips (SoCs) are a promising research area due to their improved speed (due to ...
Constant necessity of improving performance has brought the invention of 3D chips. The improvement i...
Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip comm...
Three-dimensional integrated circuits are a promising approach to address the integration challenges...
Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration c...
We propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh networ...
Floorplanning is an important physical design step for hierarchical, building-block design methodolo...
(3D-MPSoC) adoption. It is characterized by the integration of a large amount of hardware components...