Korea

Most of portable devices are required smaller size and higher performance. Au wire bonding has been used for the interconnection between stacked chips. Wire bonding can reduce footprint of packaged chip area, however it cannot reduce RC-delay due to its long wiring length. The attention on the 3D SiP has been increased to minimize signal delay and achieve high density package on small substrate. Copper via filling by electroplating method became a common technology for interlayer metallization in 3D SiP(System in Packaging). [1~4] Defects such as voids or seams are found frequently in high-aspect ratio vias when the experimental parameters were not optimized. Defect-free copper via filling is important due to the reliability issues. The void free copper via can be obtained with variation of additives of the electrolytes and other experimental parameters such as current density and current mode. Five important additives were used in acidic plating bath for the defect free copper via filling. Polyethylene glycol (PEG) was used for suppressors and bis-(3-sulfopropyl) disulfide (SPS) was used for accelerators. Janus green B (JGB) and Safranin O(SO) were also used for leveler. The effects of current mode and duty cycle on the copper via filling were also investigated. The effects of additives were investigated by several methods such as polarization plots, cyclic voltammetry plots and surface analysis of copper nucleation. Prior to copper via filling, the nucleation and growth behavior of copper with variation of additives were investigated. Plating bath composition and its functions are shown in table 1. Table 1. Bath compositions for copper via fillin