In this paper, we first present the concept of the k-th invari-ant. In contrast to the traditional invariants that hold for all cycles, k-th invariants guarantee to hold only after the k-th cycle from the initial state. We then present a bounded model checker BMChecker and an invariant prover IProver, both of which are based on circuit SAT techniques. Jointly, BMChecker and IProver are used to compute the k-th in-variants, and are further integrated with a sequential SAT solver for checking sequential equivalence. Experimen-tal results demonstrate that the new sequential equivalence checking framework can efficiently verify large industrial designs. I
Today's digital systems are at the forefront of modern technology. Electronic chips with a billion t...
One application of equivalence checking is to establish correspondence between a high-level, abstrac...
A new approach to sequential verification of designs at different levels of abstraction by symbolic ...
Checking the functional equivalence of sequential circuits is an important practical problem. Becaus...
Because general algorithms for sequential equivalence checking require a state space traversal of th...
This paper describes optimized techniques to efficiently compute and reap benefits from inductive in...
In this paper, we address the problem of verifying the equivalence of two sequential circuits. State...
In this paper, we propose a novel technique on mining rela-tionships in a sequential circuit to disc...
Abstract — Combinational equivalence checking is an essential task in circuit design. In this paper ...
Full sequential equivalence checking by state space traversal has been shown to be unpractical for l...
[[abstract]]In this paper we address the problem of verifying the equivalence of two sequential circ...
[[abstract]]In this paper, we address the problem of verifying the equivalence of two sequential cir...
This study explores the utility of reusing proven component invariants in the backward reachability-...
Iterative retiming and resynthesis is a powerful way to optimize se-quential circuits but its massiv...
128 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.We address the issue of trans...
Today's digital systems are at the forefront of modern technology. Electronic chips with a billion t...
One application of equivalence checking is to establish correspondence between a high-level, abstrac...
A new approach to sequential verification of designs at different levels of abstraction by symbolic ...
Checking the functional equivalence of sequential circuits is an important practical problem. Becaus...
Because general algorithms for sequential equivalence checking require a state space traversal of th...
This paper describes optimized techniques to efficiently compute and reap benefits from inductive in...
In this paper, we address the problem of verifying the equivalence of two sequential circuits. State...
In this paper, we propose a novel technique on mining rela-tionships in a sequential circuit to disc...
Abstract — Combinational equivalence checking is an essential task in circuit design. In this paper ...
Full sequential equivalence checking by state space traversal has been shown to be unpractical for l...
[[abstract]]In this paper we address the problem of verifying the equivalence of two sequential circ...
[[abstract]]In this paper, we address the problem of verifying the equivalence of two sequential cir...
This study explores the utility of reusing proven component invariants in the backward reachability-...
Iterative retiming and resynthesis is a powerful way to optimize se-quential circuits but its massiv...
128 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.We address the issue of trans...
Today's digital systems are at the forefront of modern technology. Electronic chips with a billion t...
One application of equivalence checking is to establish correspondence between a high-level, abstrac...
A new approach to sequential verification of designs at different levels of abstraction by symbolic ...