, Hsi-Che Tseng 1

Abstract- As the feature size of chips shrinks with semiconductor technology advancing, the size of transistors and their operating voltage keep decreasing. One of the major problems with advanced semiconductor technology is timing errors caused by process variation and noises. With such problems, conventional worst-case designs suffer poor system performance. This paper proposes an aggressive design technique for VLSI digital filters for tolerating transient timing errors. When a timing error occurs, the system reconfigures the buffer cells of digital filters with little performance degradation. We have applied the technique to two example digital filter designs, including an FIR filter and an IIR filter. The implementation results show that our proposed designs achieve tolerance of transient timing errors with reasonable cost. Index Terms – Timing errors; error-resilient design; digital filters; VLSI design. 1