A High Speed Binary Single Precision Floating Point Multiplier Using Dadda Algorithm and Parallel Prefix Adder Mr. Shailesh Kumar

Abstract--- Floating Point Arithmetic is extensively used in the field of Digital signal processing, Medical imaging, motion capture, audio application including broadcast and musical instruments.Many of these applications need to solve linear systems that use fair amount of matrix multiplication. The multiplier conforms to the IEEE 754 standard for single precision. The IEEE standard for Binary Floating point Arithmetic (IEEE 754)is most widely used standard for Floating point computation and is followed by many CPU and FPU implementation. An algorithm called Dadda algorithm is introduced here for reducing the partial product of multiplier unit single precision format. In this thesis to improve speed of multiplication of mantissa is done by using Dadda algorithm replacing carry save multiplier. The sub-module have been written in Verilog HDL and then synthesized simulated using Xilinx ISE 12.4. To find overall more speed of multiplication of two 32 bit Floating point numbers the exponents of two 32 bit Floating point numbers is calculated as Ea +Eb-127.Here exponent addition takes place by using kogge stone adder instead of Ripple carry adder which is used earlier. Earlier speed was 526 MHZ but the use of Dadda algorithm in mantissa multiplication and kogge stone adder in the exponent calculation increases the speed and reduces the delay time. So the kogge stone adder is faster adder and reduces delay. The Floating point multiplier is developed to handle overflow and underflow cases. Keywords- Dadda algorithm; Single precision Floating point number; multiplication; Verilog HDL