Multiplierless Decimation and Commercial Postfiltering of a Discrete-Time Signal

This thesis, presents the design of a digital filtering system for an analog microchip. A digital decimator is placed directly on the microchip with the analog circuitry. This decimator is a modification of the standard Cascaded Integrator Comb decimator. Further digital filtering is accomplished off-chip using Altera FLEX8000 PLDs. A technique is developed to cope with delays in first-order highpass and lowpass IIR filters. An FIR lowpass filter is modified to correct for passband attenuation caused by the decimator