We propose a depth cache that keeps the depth data in compressed format, when possi-ble. Compared to previous work, this requires a more flexible cache implementation, where a tile may occupy a variable number of cache lines depending on whether it can be compressed or not. The advantage of this is that the effective cache size increases proportionally to the compression ratio. We show that the depth-buffer bandwidth can be reduced, on average, by 17%, compared to a system compressing the data af-ter the cache. Alternatively, and perhaps more interestingly, we show that pre-cache compression in all cases increases the effective cache size by a factor of two or more, compared to a post-cache compressor, at equal or higher performance. 1
Data compression is a promising technique to address the increasing main memory capacity demand in f...
Publisher Copyright: © 2023 Copyright held by the owner/author(s).Depth maps are needed by various g...
With the widening gap between processor and memory speeds, memory system designers may find cache co...
We propose a depth cache that keeps the depth data in compressed format, when possi-ble. Compared to...
Depth buffer performance is crucial to modern graphics hardware. This has led to a large number of a...
Processors face steep penalties when accessing on-chip memory in the form of high latency. On-chip c...
This paper presents what we believe are the first (public) algorithms for floating-point (fp) color an...
The effective size of an L2 cache can be increased by using a dictionary-based compression scheme. N...
This synthesis lecture presents the current state-of-the-art in applying low-latency, lossless hardw...
Caches are essential to today's microprocessors. They close the huge speed gap between processors an...
International audienceHardware cache compression derives from software-compression research; yet, it...
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compressio...
International audienceCache compression algorithms must abide by hardware constraints; thus, their e...
In this paper, we reevaluate the use of adaptive com-pressed caching to improve system performance t...
International audienceThe effectiveness of a compressed cache depends on three features: i) th...
Data compression is a promising technique to address the increasing main memory capacity demand in f...
Publisher Copyright: © 2023 Copyright held by the owner/author(s).Depth maps are needed by various g...
With the widening gap between processor and memory speeds, memory system designers may find cache co...
We propose a depth cache that keeps the depth data in compressed format, when possi-ble. Compared to...
Depth buffer performance is crucial to modern graphics hardware. This has led to a large number of a...
Processors face steep penalties when accessing on-chip memory in the form of high latency. On-chip c...
This paper presents what we believe are the first (public) algorithms for floating-point (fp) color an...
The effective size of an L2 cache can be increased by using a dictionary-based compression scheme. N...
This synthesis lecture presents the current state-of-the-art in applying low-latency, lossless hardw...
Caches are essential to today's microprocessors. They close the huge speed gap between processors an...
International audienceHardware cache compression derives from software-compression research; yet, it...
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compressio...
International audienceCache compression algorithms must abide by hardware constraints; thus, their e...
In this paper, we reevaluate the use of adaptive com-pressed caching to improve system performance t...
International audienceThe effectiveness of a compressed cache depends on three features: i) th...
Data compression is a promising technique to address the increasing main memory capacity demand in f...
Publisher Copyright: © 2023 Copyright held by the owner/author(s).Depth maps are needed by various g...
With the widening gap between processor and memory speeds, memory system designers may find cache co...