Add to ORKGComplexity analysis of the cost-table approach to the design of multiple-valued logic circuit
We survey complexity results concerning a family of propositional many-valued logics. In particular,...
Multiple-valued logic (MVL) circuits can be designed and implemented, utilizing 4 levels of logic, i...
Multiple-valued logic minimization is an important technique for reducing the area required by a Pro...
Abstract—We analyze the computational complexity of the cost-table approach to designing multiple-va...
Abstruct- We propose a heuristic for finding minimal cost-tables for use in the design of multiple-v...
We propose an algorithm for ihe design of multiple-valued current-mode CMOS logic (CMCL) circuiis th...
The paper describes the main issues in logic optimization of multi-valued multi-level logic networks
We address optimizing multi-valued (MV) logic functions in a multi-level combinational logic network...
Over the last two decades, design using Multiple-Valued Logic (MVL) has been receiving considerable ...
Abstract — In this paper, we report on initial experiments on the feasibility of a circuit design ap...
The procedures and methods presented in this dissertation are completely general, systematic, and ea...
In the last decade, we have seen how Moore's law has lost its validity because it has reached the ph...
We propose a novel method to estimate the complexity of multiple-valued logic functions based on fun...
The Multiple valued logic(MVL) has increased attention in the last decades because of the possibilit...
Abstract: A three-level programmable logic array (three-level PLA) consists of three main parts, the...
We survey complexity results concerning a family of propositional many-valued logics. In particular,...
Multiple-valued logic (MVL) circuits can be designed and implemented, utilizing 4 levels of logic, i...
Multiple-valued logic minimization is an important technique for reducing the area required by a Pro...
Abstract—We analyze the computational complexity of the cost-table approach to designing multiple-va...
Abstruct- We propose a heuristic for finding minimal cost-tables for use in the design of multiple-v...
We propose an algorithm for ihe design of multiple-valued current-mode CMOS logic (CMCL) circuiis th...
The paper describes the main issues in logic optimization of multi-valued multi-level logic networks
We address optimizing multi-valued (MV) logic functions in a multi-level combinational logic network...
Over the last two decades, design using Multiple-Valued Logic (MVL) has been receiving considerable ...
Abstract — In this paper, we report on initial experiments on the feasibility of a circuit design ap...
The procedures and methods presented in this dissertation are completely general, systematic, and ea...
In the last decade, we have seen how Moore's law has lost its validity because it has reached the ph...
We propose a novel method to estimate the complexity of multiple-valued logic functions based on fun...
The Multiple valued logic(MVL) has increased attention in the last decades because of the possibilit...
Abstract: A three-level programmable logic array (three-level PLA) consists of three main parts, the...
We survey complexity results concerning a family of propositional many-valued logics. In particular,...
Multiple-valued logic (MVL) circuits can be designed and implemented, utilizing 4 levels of logic, i...
Multiple-valued logic minimization is an important technique for reducing the area required by a Pro...