Application-Specific Optical Interconnects for Embedded Multiprocessors

Abstract — As transistor sizes shrink and we approach the “end of Moore’s law”, interconnects—both on-chip and off-chip—will represent the biggest bottleneck for embedded systems designers. Several groups are research-ing optical interconnects to cope with this trend. Optical interconnects enable new system architectures. These new architectures in turn require new methods for high-level application mapping and hardware/software co-design. In this presentation, we discuss high-level scheduling and interconnect topology synthesis techniques for embedded multiprocessors. We focus on designs that are streamlined for one or more digital signal processing (DSP) applica-tions. That is, we seek to synthesize an application-specific interconnect topology for a multiprocessor DSP design. We show that flexible interconnect topologies that allow single-hop communication between processors offer advantages for reduced power and latency. We have previously shown that multiprocessor schedul-ing algorithms can deadlock in the general case of a topology graph that is not strongly connected, or if communication is limited to be single hop. We have also demonstrated an efficient algorithm that can be used in conjunction with existing scheduling algorithms for avoiding this deadlock [1]. In this presentation we discuss the advantages of performing application scheduling and interconnect synthesis jointly, and present a probabilistic scheduling/interconnect algorithm utilizing graph isomor-phism to pare the design space. We demonstrate the perfor-mance advantages that an application-specific interconnect topology can produce for several DSP benchmarks. Index Terms — interconnect synthesis, multiprocessor, scheduling. I