Efficient Implementation of Decimal Floating Point Adder in FPGA

Decimal floating Point adder is one of the most frequent operations used by many financial, business and user-oriented applications but current implementations in FPGAs are very inefficient in terms of both area and latency when compared to binary floating point adder. This paper has shown an efficient implementation of a new parallel decimal floating point module on a reconfigurable platform, which is both area as well as performance optimal. The decimal floating-point Adder was further pipelined into five stages to increase the maximum frequency of operation. The synthesis results for a Stratix IV device indicate that our implementations have 25.1 % reduction of the latency and 1.1 % reduction of area compared to an existing alter-core adder design, presenting area and delay figures close to those of optimal binary adder trees