Global design of analog cells using statistical optimization techniques. Analog integrated circuits and signal processing

We present a methodology for automated sizing of analog cells using statistical optimi-zation in a simulation based approach. This methodology enables to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this perfor-mance, and design objectives. A mathematical cost function is proposed and a bunch of heuris-tics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance param-eters, under random variations of the transistor technological parameters. Several CMOS ana-log cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology