A Single-Bit Digital DC-Blocker Using Ternary Filtering

In this paper, a single-bit dc-blocker is presented. It is comprised of a ternary ifitering stage preceded by a sigma-delta modulator. Different techniques are used to generate the ternary taps for hardnare and performance optimization. Both the input and the output of this dc-blocker are assumed in single-bit format. The proposed dc-blocker can easily be implemented with FPGA