ESTIMATION-THEORETIC FRAMEWORK FOR ROBUST AND ENERGY-EFFICIENT SYSTEM DESIGN BY

A fundamental hurdle to realizing the exciting future applications of embedded computing is lack of adequate power supply. Unlike the exponential growth in computing capability, the improvements in power sources have been lackluster. Technology scaling, driven by Moore’s law, has produced smaller devices that can operate on lower supply voltages; but as a side effect, nanoscale devices are becoming increasingly unreliable. The resulting increase in transistor density further exacerbates the power problem. Therefore, the computing industry faces a pressing need to aggressively reduce power consumption and efficiently address error resiliency. Conventional approaches to error resiliency using redundant computations have incurred the associated overheads of power and silicon area. Traditional power reduction techniques scale supply voltage or clock frequency to adapt to changing demands of the application, while bein