Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array

Linear feedback shift registers (LFSRs) are common structures in many application fields, including cryptog-raphy, digital broadcasting and communication. High-throughput requirements need highly parallel implementa-tions, usually accomplished in state of the art system on chips (SoCs) with application specific coprocessors. Al-though this approach achieves the required performance, it rapidly shows lack of flexibility when those devices are proposed, as an example, for multi-standard modems or for security applications in which run-time update can provide added value. This paper shows the implementation of paral-lel LFSR-based applications on an embedded adaptive DSP featuring a Pipelined Configurable Gate Array (PiCoGA). With respect to standard embedded FPGAs, pipelined de-vices usually provide better performance, e.g. in terms of speed, but they commonly show the undeniable drawback of additional design constraints. As a test-case, we consider the implementation of the 32-bit CRC used in the Ether-net standard that achieves on the target architecture up to 25Gbit/sec throughput, with a parallel LFSR processing 128 bit at time, which is comparable to the performance offered by some ASIC devices. 1