We consider the product design problem of allocating the chip sites on a semiconduc-tor wafer to various types of chips. The manufacturing facility sells chips to its customers in sets (a specified number of several different types of chips), and the objective of the facility is to maximize the average production rate of sets. Variabilitj ' in the wafer fab-rication process, in particular random yield, poses a major obstacle in producing sets in a reliable fashion. A stochastic analysis is employed to develop an effective wafer de-sign, and to measure the improvement in performance of the multi-type wafer over the traditional single-type wcifer. The analysis reveals that multi-type wafers regularize the production flow of non-defective...
Vita.This dissertation deals with both theoretical and practical aspects of integrated circuits (IC'...
Abstract—Conventionally, people focus on defect reduction to improve yield rate. Little research has...
can speed rush lots Reducing cycle time is a key component of any fab manager’s task. J. Blanc and S...
This paper focuses on a lot merging/splitting problem in a semiconductor wafer fabrication facility....
Includes bibliographical references (p. 41-42).Supported by a grant from the Leaders for Manufacturi...
A simple approach for CMOS integrated circuit (IC) design taking into account a process variability ...
An interactive environment is presented for the analysis of yield information required on modern int...
Abstract—This paper focuses on production scheduling in a semiconductor wafer fab producing multiple...
Integrated circuit size (and hence complexity) is limited by the fact that chips created using curre...
One problem in semiconductor manufacturing optimization is to find an optimal release rate of raw ma...
Recently, there has been increasing interest in the problem of wafer placement on a chip grid with t...
The pervasive use of advanced reticle enhancement technologies demanded by VLSI technology scaling l...
The pervasive use of advanced reticle enhancement technologies demanded by VLSI technology scaling l...
This paper discusses the development of an efficient algorithm that minimizes overproduction in the ...
This paper studies the problem of allocating semiconductor wafers to customer orders with the object...
Vita.This dissertation deals with both theoretical and practical aspects of integrated circuits (IC'...
Abstract—Conventionally, people focus on defect reduction to improve yield rate. Little research has...
can speed rush lots Reducing cycle time is a key component of any fab manager’s task. J. Blanc and S...
This paper focuses on a lot merging/splitting problem in a semiconductor wafer fabrication facility....
Includes bibliographical references (p. 41-42).Supported by a grant from the Leaders for Manufacturi...
A simple approach for CMOS integrated circuit (IC) design taking into account a process variability ...
An interactive environment is presented for the analysis of yield information required on modern int...
Abstract—This paper focuses on production scheduling in a semiconductor wafer fab producing multiple...
Integrated circuit size (and hence complexity) is limited by the fact that chips created using curre...
One problem in semiconductor manufacturing optimization is to find an optimal release rate of raw ma...
Recently, there has been increasing interest in the problem of wafer placement on a chip grid with t...
The pervasive use of advanced reticle enhancement technologies demanded by VLSI technology scaling l...
The pervasive use of advanced reticle enhancement technologies demanded by VLSI technology scaling l...
This paper discusses the development of an efficient algorithm that minimizes overproduction in the ...
This paper studies the problem of allocating semiconductor wafers to customer orders with the object...
Vita.This dissertation deals with both theoretical and practical aspects of integrated circuits (IC'...
Abstract—Conventionally, people focus on defect reduction to improve yield rate. Little research has...
can speed rush lots Reducing cycle time is a key component of any fab manager’s task. J. Blanc and S...