Low Power High Speed 64 Bit SRAM Architecture using SCCMOS and Drowsy Cache Concept

With the development of technology with each passing days, the demand for low power, high speed, high density memory for portable devices is increasing proportionally. The power consumption and battery life has become the major concerns for VLSI industry. But as the technology scales down it gives rise to an unwanted parameter i.e., the leakage power which according to International technology roadmap of semiconductors (ITRS) will dominate the majority part of the total power consumption.In this paper a complete 64 bits SRAM array is designed using the leakage power reduction techniques.2 techniques are being combined which are sleep stack with keeper and other is the drowsy cache including the SCCMOS concept.The array is designed and simulated using cadence gpdk 180nm technology.The results show that the total power consumption has reduced by nearly 40 % for 1 bit SRAM along with its peripheral