0013-4651/2013/160(12)/D3211/5/$31.00 © The Electrochemical Society JES FOCUS ISSUE ON ELECTROCHEMICAL PROCESSING FOR INTERCONNECTS PVD Cu Reflow Seed Process Optimization for Defect Reduction in Nanoscale Cu/Low-k Dual Damascene Interconnects

A novel Cu reflow seed process which utilizes physical vapor deposition (PVD) technology components has been demonstrated for nanoscale dual damascene interconnects. Prior to Cu electroplating, small features can be partially filled with Cu by this newly developed Cu reflow seed process. It is confirmed that both suitable seed coverage and appropriate reflow temperature are required for achieving ideal reflow property. Bias conditions during Cu PVD dominate seed coverage in features, and processes at moderate bias are demonstrated to provide optimum bottom and sidewall coverage, while limiting field coverage. Overall Cu fill performance was enhanced significantly and more than a 60 % improvement in via-chain yield is obtained by Cu reflow seed compared to conventional seed. Furthermore, Cu lines with fewer voids and less impurities are fabricated by repeating this Cu reflow seed process several times to obtain complete feature fill, which results in lower leakage current between lines. This Cu reflow seed process is a promising candidate for improving Cu fill performance for nanoscale Cu/low-k interconnects of 32 nm critical dimension and beyond