Semiconductor manufacturing is a highly complex and re-entrant process. In a fabrication facility, hundreds of decisions are made during a production shift regarding how shared tool capacity will be prioritized. These decisions contribute to how balanced or unbalanced the manufacturing line will be. Characteristics of an unbalanced line are large WIP bubbles, long queue times, and expediting. A balanced line has less WIP bubbles, shorter queues, and WIP is positioned at all points throughout the line to be in position to meet the demand forecasted. This thesis focuses on work performed at Intel's Fab 23 to improve the process for assigning production priorities through the introduction of pull methodologies. Existing processes and tool...
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Mechanical Engineering, 2017.T...
This thesis is a description of an internship project at an aerospace parts distribution company. Th...
Mean cycle time, standard deviation of the cycle time, WIP level, throughput, and due date performan...
Thesis (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; and, (S.M.)--Mas...
Semiconductor manufacturing is a complex, non-linear process. The processing order of wafer lots in ...
High inventory holding costs and the competition of lead time are concerns of a food packaging manuf...
A new algorithm is developed for setting WIP level in production lines. It is a pull policy that de...
Thesis: M. Eng. in Manufacturing, Massachusetts Institute of Technology, Department of Mechanical En...
The widespread implementation of lean in discrete manufacturing has changed the face of those busine...
The Factory Operations portion of the 2001 International Technology Roadmap for Semiconductors (ITRS...
A good manufacturing practice for production assembly can result in better productivity for the orga...
In this paper, a scheduling heuristic was developed to aid the operators in semiconductor fabs in ch...
The production lines become more and more complex with increasing demands from mass production to cu...
In this paper, a scheduling heuristic was developed to aid the operators in semiconductor fabs in ch...
: This paper describes a novel pull system based on value stream mapping (VSM) in an electronics ass...
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Mechanical Engineering, 2017.T...
This thesis is a description of an internship project at an aerospace parts distribution company. Th...
Mean cycle time, standard deviation of the cycle time, WIP level, throughput, and due date performan...
Thesis (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; and, (S.M.)--Mas...
Semiconductor manufacturing is a complex, non-linear process. The processing order of wafer lots in ...
High inventory holding costs and the competition of lead time are concerns of a food packaging manuf...
A new algorithm is developed for setting WIP level in production lines. It is a pull policy that de...
Thesis: M. Eng. in Manufacturing, Massachusetts Institute of Technology, Department of Mechanical En...
The widespread implementation of lean in discrete manufacturing has changed the face of those busine...
The Factory Operations portion of the 2001 International Technology Roadmap for Semiconductors (ITRS...
A good manufacturing practice for production assembly can result in better productivity for the orga...
In this paper, a scheduling heuristic was developed to aid the operators in semiconductor fabs in ch...
The production lines become more and more complex with increasing demands from mass production to cu...
In this paper, a scheduling heuristic was developed to aid the operators in semiconductor fabs in ch...
: This paper describes a novel pull system based on value stream mapping (VSM) in an electronics ass...
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Mechanical Engineering, 2017.T...
This thesis is a description of an internship project at an aerospace parts distribution company. Th...
Mean cycle time, standard deviation of the cycle time, WIP level, throughput, and due date performan...